CommScope, Inc. Engineer, Senior, FPGA in Forest, Virginia
Everyone communicates. It’s the essence of the human experience. How we communicate is evolving. Technology is reshaping the way we live, learn and thrive. The epicenter of this transformation is the network—our passion. Our experts are rethinking the purpose, role and usage of networks to help our customers increase bandwidth, expand capacity, enhance efficiency, speed deployment and simplify migration. From remote cell sites to massive sports arenas, from busy airports to state-of-the-art data centers— we provide the essential expertise and vital infrastructure your business needs to succeed. The world’s most advanced networks rely on CommScope connectivity.
The Senior FPGA Engineer is responsible for architecture, design, implementation, and integration of RTL for radio products. Design functions will include Multi-Gig Serdes, LTE Physical Layer, fronthaul compression, and baseband quadrature signal processing. Architecture activities will involve concept development, design partitioning, device sizing/selection, and workload estimation for FPGA tasks. The engineer will participate with Hardware and Software engineers for bring up, design verification testing (DVT) and end-to-end integration.
Duties & Responsibilities:
Bachelor in Electrical Engineering with 8+ or Master in Electrical Engineering with 5+ years of experience.
Architects digital systems for use in wireless communication networks.
Designs, simulates, and implements LTE Layer 1 in an FPGA.
Designs, simulates, and implements data compression functionality.
Works closely with RF and SW teams for design and integration, as well as debug and test/validation.
Provides mentorship to junior engineers as a subject-area expert.
Maintains revision control of FPGA release code base. Xilinx Vivado synthesizer Matlab and Simulink.
Model based design tools such as Xilinx System Generator, DSP Builder
Digital Signal Processing for RF such as Digital NCO, Quadrature modulator and demodulator, Channel filtering, FFT/iFFT, AGC and PLL filters
Clock domain partitioning, timing constraints rules, static timing closure.
Hierarchical test bench design.
Automated vector stimulus input and output pass/fail checking
Strong communication skills, and demonstrated ability to work in multi-site and multi-discipline engineering environments.
Working knowledge of SoC-based FPGAs involving MC-DMA and AXI interconnect for high-speed data processing. ChipScope/SignalTap debugger or equivalent method experience
It is the policy of CommScope to provide Equal Employment Opportunities to all individuals based on merit, qualifications and abilities. CommScope does not discriminate in employment opportunities or practices on the basis of race, color, religion, gender (including pregnancy), national origin, age or any other characteristics as protected by law. Furthermore, this contractor and subcontractor shall abide by the requirements of 41 CFR 60-300.5(a) and 41 CFR 60-741.5(a). These regulations prohibit discrimination against qualified protected veterans and qualified individuals on the basis of disability, and require affirmative action by covered prime contractors and subcontractors to employ and advance in employment qualified protected veterans and qualified individuals with disabilities.